With the miniaturized, portable, ultra-thin, multi-media and low cost-oriented development of electronic products such as mobile phones, laptops, etc., high-density, high-performance, high-reliability and low-cost package forms and the assembly technology have been developed rapidly. Compared with expensive packages such as BGA and the like, in recent years, the novel package technology have developed rapidly (that is, QFN package (Quad Flat Non-lead Package)). As they have the advantages of good thermal and electrical performance, small size, low cost, high productivity, etc., a new revolution in the field of microelectronics packaging technology is introduced.
FIG. 1A is a diagram illustrating bottom view of conventional QFN package. FIG. 1B is a diagram illustrating a cross-section view of conventional QFN package along line I-Í of FIG. 1A. Conventional QFN package 100 includes a leadframe 11, a plastic mold material 12, an adhesive material 13, an IC chip 14 and a plurality of metal wires 15, wherein leadframe 11 comprises a chip pad 111 and a plurality of leads 112 arrayed around chip pad 111. IC chip 14 is attached to chip pad 111 via adhesive material 13. IC chip 14 is electrically connected with leads 112 via metal wires 15. IC chip 14, metal wires 15 and leadframe 11 are molded utilizing plastic mold material 12 for protection and support. Leads 112 exposed at the bottom surface of plastic mold material is soldered to printed circuit board (PCB not shown) to provide electrical connection with outside. Exposed chip pad 111 is soldered to printed circuit board (PCB not shown) to provide an excellent heat dissipation channel to release heat produced by IC chip 14. Compared with TSOP and SOIC packages, QFN package does not have a gull-wing shaped lead and has a short conductive path, low self-inductance coefficient and low impedance, thus providing sound electrical performance and meeting high-speed or microwave application requirement.
With the demand of high integration, high performance, high reliability and low cost of electronic devices, high lead number, and high reliability as well as low cost of electronic packages are required. However, conventional QFN package described before has some drawbacks, and cannot meet the requirements. As shown in FIG. 1A of conventional QFN package 100, just only a single row of leads 112 are arrayed around chip pad 111, thus limiting the number of leads 112. As shown in FIG. 1B of conventional QFN package 100, leadframe 11 are effectively locked by mold material 12, resulting in poor adhesion between leadframe 11 and mold material 12, easily causing delamination failure, and even causing chip pad 111 and leads 112 to fall off. Furthermore, moisture may not be effectively prevented from diffusing into inside along the interface between leadframe 11 and mold material 12. During the molding process of conventional QFN package 100, an adhesive tape is required to paste on the bottom of leads 11 in advance to prevent overflow problem. After molding process, it is needed to remove the adhesive tape, thus increasing the manufacturing cost. During the sawing process of conventional QFN package 100, a blade saws the metal of leadframe 11 as well as mold material 12, thus not only lowering the sawing process efficiency and shorting the life of the blade, but also resulting in metal burrs problem. Therefore, in order to break through the bottleneck of the low density, improve the reliability and reduce the manufacturing cost of conventional QFN package, it is an urgent need to develop an advanced QFN package having the advantages of high reliability, low cost and high density, and a manufacturing method thereof.